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fedl9488-01 issue date: jan. 15, 2013 ML9488 static, 1/2 duty, 1/3 duty, 1/4 duty 80 outputs lcd driver 1/31 general description the ML9488 is an lcd driver lsi, consists of a 80-bit shift register, a 320-bit data latch, 80 sets of lcd drivers, and a common signal generation circuit. it can directly drive an lcd up to 80 segments for static display, 160 segments for 1/2-duty display, 240 segments for 1/3-duty display, and 320 segments for 1/4-duty display. the three-wire serial interface and i 2 c interface are selectable. features ? ? logic power supply voltage : 2.7 to 5.5 v ? lcd drive power supply voltage : 4.5 to 5.5 v ? maximum number of segments static display : 80 segments 1/2-duty display : 160 segments 1/3-duty display : 240 segments 1/4-duty display : 320 segments ? interface with microcomputer : serial interface : data, clock, load clock transfer speed up to 1 mhz i 2 c interface : sda, scl, sdaack scl transfer speed up to 400 khz ? built-in cr oscillator circuit using the internal resistor or external resistor ? cascade connectable (up to sixteen chips) ? built-in common signal generation circuit ? built-in common output intermediate-value voltage generation circuit ? built-in poc (power on clear) circuit ? gold bump chip (ML9488dvwa) ? comparison table item ml9478cdvwa ML9488dvwa frame frequency (internal oscillation) 65hz/75hz/85hz/95hz (programmable) 130hz/150hz/170hz/190hz (programmable)
fedl9488-01 ML9488 2/31 block diagram 80-dot segment driver latch selector load osc latch1 latch2 dat a sd a clock scl bias vdd gnd timing generator 80-ch data selector common driver seg1 seg80 com1 80-bit shift register 80-bit 80-bit 80 com2 com3 com4 duty0 80 80 80 80 vlcd bias resi. osc i/e oscr osc1 osc2 duty1 latch4 80-bit 80-bit latch3 resetb command decoder sdaack sa1 a1 a0 cko syncb m/s poc circuit i2c test1 test2 poceb sa0
fedl9488-01 ML9488 3/31 absolute maximum ratings item symbol condition rating unit logic power supply voltage v dd ta = 25c -0.3 to 6.0 v lcd drive power supply voltage v lcd ta = 25c - 0.3 to 6.0 v input voltage v i ta = 25c ? 0.3 to v dd + 0.3 v output short-circuit current is ta = 25c - 2.0 to +2.0 ma chip temperature tc ? 125 c storage temperature t stg ? -55 to +150 c note: do not use the ML9488 by short-circuiting one output pin to another output pin as well as to other pin (input pin, input/output pin, or power supply pin). recommended operation conditions item symbol condition range unit logic power supply voltage v dd * ? 2.7 to 5.5 v lcd drive power supply voltage v lcd * ? 4.5 to 5.5 v osc in clock frequency f cp1 ? up to 10 khz data clock frequency f cp2 ? up to 1.0 mhz scl clock frequency f scl ? up to 400 khz operating temperature t a ? -40 to +105 c note(*): use at v dd ? v lcd . the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 recommended setting range for external component (oscillator circuit) (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= ?40 to +105c) item symbol condition min typ max unit oscillation resistor r f ? 423 470 517 k ? frame frequency f frm (f1,f0)=(0,1) 47 75 114 hz the relation between oscillation resistor and frame frequency is as the equation below. f frm = f osc /(8 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25%
fedl9488-01 ML9488 4/31 electrical characteristics dc characteristics (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin "h" input voltage v ih ? 0.8v dd ? v dd v (*1) "l" input voltage v il ? gnd ? 0.2v dd v (*1) input leakage current 1 i l1 v i = v dd or 0 v -1.0 ? 1.0 a (*1) input leakage current 2 i l2 v i = v dd or 0v poceb="h" -1.0 ? 1.0 a resetb pull-up current i pu v dd = 5.0v,v i = 0 v poceb = "l" 30 ? 140 a resetb "h" output voltage v oh i o = -600ua 0.9v dd ? ? v ? cko, syncb "l" output voltage 1 v ol1 i o = 600ua ? ? 0.1v dd v cko, syncb "l" output voltage 2 v ol2 i o = 600ua ? ? 0.1v dd v sdaack segment v ohs v lcd = 5v ? 5 15 k ? seg1 to seg80 driver on resistor common v ohc v lcd = 5v ? 5 12 k ? com 1 to com4 (*1) : data(sda), clock(scl), load, m/s, syncb, duty1, duty0, bias, sa1,sa0, a1, a0, osc1, osc i/e, i2c, poceb (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta= -40 to +105c) item symbol condition min. typ. max. unit applicable pin i dds ? 8 15 a vdd static supply current i lcds v dd =v lcd =5.5 v input pin fixed to "h" or "l" oscillation stopped, output no-load poceb="l" ? 9 15 a vlcd i dd1 (*6) ? 11 20 a vdd dynamic supply current 1 i lcd1 v dd =v lcd = 5.5 v (*2)(*3) clock osc1 external input f cp1 =1.8khz (*7) ? 10 17 a vlcd i dd2 (*6) ? 62 92 a vdd dynamic supply current 2 i lcd2 v dd =v lcd = 5.5 v (*2)(*3) internal oscillation (*7) ? 10 17 a vlcd i dd3 ? 131 252 a vdd dynamic supply current 3 i lcd3 v dd =v lcd = 5.5 v (*2)(*4)(*6) internal oscillation at three-wire serial if data input ? 10 17 a vlcd i dd4 ? 203 332 a vdd dynamic supply current 4 i lcd4 v dd =v lcd = 5.5 v (*2)(*5)(*6) internal oscillation at i 2 c if data input ? 10 17 a vlcd (*2) : m/s = "h", 1/4-duty, 1/3-bias, (f1,f0) = (1,1) 190 hz, poceb = "l", output pin no-load. (*3) : three-wire serial or i 2 c interface. input pin fixed to "h" or "l". (*4) : serial interface, data input frequency = 1 mhz. (*5) : i 2 c interface, data input frequency = 400 khz. (*6) : alternately inputs "0" and "1" for lcd display data (checkered display). (*7) : inputs all "1s" for lcd display data (all illuminated).
fedl9488-01 ML9488 5/31 switching characteristics ? osc ti ming (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin osc in clock frequency (external input) f cp1 ? 1.8 10 khz osc1 clock pulse width (external input) t wcp1 40 ? ? s osc1 clock rise and fall time (external input) t osc clock input from osc1. osc2 and oscr open. osc i/e = "l" ? ? (*1) s osc1 external rf clock frequency (internal oscillation) f osc1 between osc1 and osc2 r f = 470k ? (f1,f0)=(0,1) oscr open. osc i/e = "h" 18 28.8 44 khz osc1, osc2 internal clock frequency (internal oscillation) f osc2 osc1 open. (f1,f0)=(0,1) osc2 and oscr short-circuited. osc i/e = "h" 18 28.8 44 khz osc1, oscr, osc2 the relation between osc in clock frequency and frame frequency is as the equation below. f frm = f osc /24 (*1) t osc is a reference value. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=2 s. ? serial interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin data clock frequency f cp2 ? ? 1 mhz clock data clock pulse width t wcp2 100 ? ? ns clock data setup time t su 50 ? ? ns data data hold time t hd 50 ? ? ns clock clock-load timing t cl 100 ? ? ns clock load-clock timing t lc 100 ? ? ns load load pulse width t wld 100 ? ? ns load signal rise and fall time tsr,tsf ? ? (*2) ns ? clock,data, load (*2) tsr and tsf shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=10ns.
fedl9488-01 ML9488 6/31 ? i 2 c interface timing (v dd = 2.7 to 5.5 v, v lcd = 4.5 to 5.5 v, ta = -40 to +105c) item symbol condition min. typ. max. unit applicable pin scl clock frequency f scl ? ? 400 khz scl hold time (repeat) "statrt" condition t hd,sta 0.6 ? ? s scl,sda scl "l" pulse width t low 1.3 ? ? s scl scl "h" pulse width t high 0.6 ? ? s scl setup time for repeat "start" condition t su,sta 0.6 ? ? s scl,sda data hold time t hd,dat 0 ? ? ns scl,sda data setup time t su,dat 200 ? ? ns scl,sda setup time for "stop" condition t su,sto 0.6 ? ? s scl,sda bus free time between "stop" condition and "start" condition t buf 1.3 ? ? s scl data valid acknowledge time t vd,ack ? ? 1.2 s scl,sdaaack signal rise and fall time tir,tif ? ? (*3) s ? scl,sda data bus load capacitance cb ? ? 400 pf sda,sdaack noise pulse width tolerance t wf ? ? 50 ns scl,sda (*3) tir and tif shall be reference values. the longer the clock rise and fall time, the more suscep tible to extraneous noises around the threshold value. make the rise as steep as possible. reference value: max=0.1 s.
fedl9488-01 ML9488 7/31 timing chart (osc1) osc1 (external clock) 1/f cp1 t wcp1 t wcp1 v ih v ih v il v il v ih t os c timing chart (serial interface) v ih v il v ih v il data clock v ih v ih v il v il v il v il load v ih v ih v il v il t wcp2 t wcp2 t hd t su 1/f cp2 t cl t lc t wld v ih v il t sf v ih v il t sr v ih t sr v ih v il t sf t sf t sr timing chart (i 2 c interface) t buf t low t vd;ack t r t f t hd;sta t hd;dat t high t su;dat t su;sto t su;sta sda scl sda v ih v il v ih v ih v il v ih v il v ih v ih v ih v ih v ih v il v il v il v il v il v ih v il
fedl9488-01 ML9488 8/31 reference data frame frequency characteristics vdd=5.5v/2.7v rf=470k ? frame frequency f frm = f osc /(8 x 24) fosc = 1 / (device coefficient x external resistor r f ) device coefficient = 73.8 x 10 -12 25% frame frequency characteristics rf=470k,vdd=5.5v 100 120 140 160 180 200 220 240 -60 -40 -20 0 20 40 60 80 100 120 temp ta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0) frame frequency characteristics rf=470k,vdd=2.7v 100 120 140 160 180 200 220 240 260 -60 -40 -20 0 20 40 60 80 100 120 tempta[] frame frequency ffrm[hz] (f1,f0)=(1,1) (f1,f0)=(1,0) (f1,f0)=(0,1) (f1,f0)=(0,0)
fedl9488-01 ML9488 9/31 power on/off timing to turn on the power supply, raise the logic power supply first, then lcd drive power supply in order to prevent the ic from malfunctioning. to fall the power supply, fall the lcd drive power supply first, then the logic power supply. for a vdd pin ranging from 0 v to vddmin, set vdd vlcd and t1 0 [ns]. to enable the internal poc circuit, the vdd power supply rise time t2 range needs to be 100 [s] ?? t2 ?? 500 [ms]. for the vdd power supply to turn off then turn on again, it is necessary to secure the poc discharge time t3 ?? 100 [ms]. initialization signal timing when resetb signal is externally input the resetb pin input is valid both for poceb = "l" and "h". usable in combination with the poc. keep the resetb pin at "l" level until the vdd reaches vddmin. (t4 200[ns]) when internal poc circuit is used w hen using the internal poc circuit in the initialization, set the poceb pin to "l". leave the resetb pin open. v dd v lcd time voltage t1 t1 0.9v dd t2 v dd t3 v dd resetb vil t4 v dd min
fedl9488-01 ML9488 10/31 pin descriptions pad number symbol i/o description 67-68 m/s i this is the input to switch between the master and slave modes. it has a schmitt circuit. when this pin is "h", the mode is master. when this pin is "l", the mode is slave. 6-7 4-5 duty0 duty1 *1 i display duty switch pins. these have schmitt circuits. duty0="l", duty1="l" : static (com1=com2=com3=com4) duty0="h", duty1="l" : 1/2duty (com1=com3, com2=com4) duty0="l", duty1="h" : 1/3duty (com2=com4) duty0="h", duty1="h" : 1/4duty 73-74 bias i this pin sets the lcd bias. it has a schmitt circuit. bias="l": 1/3bias bias="h": 1/2bias when the static mode selection, fix this pin at ?h? or ?l? level. 14-15 12-13 sa1 sa0 i slave address input pins. these have schmitt circuits. 10-11 8-9 a1 a0 i sub address input pins. these have schmitt circuits. 71-72 osc i/e i this input selects whether to use the external clock input mode or to use the internal oscillation mode or external oscillation mode. it has a schmitt circuit. when this pin is "h", the mode is the internal or external rf oscillation mode. when this pin is "l", the mode is the external clock input mode. use the slave chip as it is connected to gnd. 46-48 53-55 49-52 osc1, oscr, osc2 *2 i i o these pins are for the oscillator circuit to generate common signals. the osc1 and oscr pins are input pins and have a schmitt circuit. osc2 is an output pin. it becomes an output when the osc i/e pin = "h" and a high impedance when the osc i/e pin = "l". in the master mode (m/s pin ="h") three types are selectable: internal oscillation mode, external oscillation mode, and external clock input mode. ?internal oscillation mode: set the osc i/e pin to "h", short the oscr and osc2 pins, and open the osc1 pin. ?external rf oscillation mode: set the osc i/e pin to "h", connect an oscillation resistor rf between the osc1 and osc2 pins, and open the oscr pin. ?external clock input mode: set the osc i/e pin to "l", open the oscr and osc2 pins, and input the external clock to the osc1 pin. in the slave mode (m/s pin ="l") open the oscr and osc2 pins and connect the osc1 pin to the ML9488's cko pin that has been set to the master mode. 56-56 cko o clock output pin. in the master mode (m/s pin = "h"), the 1/16 division signal of the oscillation frequency is output. in the slave mode (m/s pin = "l"), the output is fixed to "l". for a cascade connection, connect this pin to the osc1 pin of the chip that has been set to the slave mode.
fedl9488-01 ML9488 11/31 60-63 syncb i/o input/output pin for common synchronization. it has a schmitt circuit. it becomes the synchronization signal output pin in the master mode (m/s pin = "h"). it becomes the synchronization signal input pin in the slave mode (m/s pin = "l"). for cascade connection, connect all of the involved ML9488s' sync pins by the common line. 65-66 i2c i interface switching pin. it has a schmitt circuit. when this pin is "h", the interface is i 2 c. when this pin is "l", the interface is three-wire serial. 20-21 data (sda) i display data input pin. it has a schmitt circuit. i2c="l": serial interface; data input the display data in the order of seg80, seg79, ... , seg2, and seg1. the display data turns on at "h" and turns off at "l". i2c="h": i 2 c interface; sda input the display data in units of 8 bits. the display data turns on at "h" and turns off at "l". this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 22-23 clock (scl) i shift clock input pin for display data. it has a schmitt circuit. i2c="l": serial interface; clock the display data input to the data pin is serially input to the shift register at the clock signal rise. i2c="h": i 2 c interface; scl the display data input to the sda pin is serially input to the shift register at the scl signal rise. this pin has a built-in noise filter through which noises in widths up to 50 ns are removed. this noise filter is valid only when i2c = "h". 24-25 load i input pin for the load signal of display data. it has a schmitt circuit. i2c="l": serial interface; load the display data in the shift register is transmitted as is to the segment driver for the "h" duration. when this pin is brought into "l", the shift register is disconnected from the segment driver. the display data in the shift register immediately before it become "l" is held in the data latch and transmitted to the segment driver. i2c="h": i 2 c interface use this pin as it is connected to gnd. 17-19 sdaack o i2c="l": serial interface use this pin as it is opened. i2c="h": i 2 c interface the i 2 c bus acknowledge output signal. normally, use it as it is connected with the sda pin. connect an external pull-up resistor whenever necessary, as it is an open drain pin. the pull-up connection destination supply voltage shall be the v dd supply voltage or less. 69-70 poceb i internal poc circuit enable pin. it has a schmitt circuit. when this pin is "h", the poc circuit becomes off and the constant current (8a) is cut. the resetb pin pull-up resistor is cut as well. when this pin is "l", the poc circuit becomes on. the resetb pin is connected to a pull-up resistor. 44-45 resetb *3 i reset signal input pin for initializing inside the ic. it has a schmitt circuit. the "l" level enables the reset. this pin has an internal pull-up resistor. when poceb = "h", input the external reset signal to this pin. when poceb = "l", the power-on reset operation is available by open this pin.
fedl9488-01 ML9488 12/31 77-78 75-76 test1 test2 i pin for testing the ic. it has an internal pull-down resistor. use it as it is connected to gnd. 95-134 139-178 seg1 ? seg80 o outputs for lcd display. connected to the segment pins on the lcd panel. in the display off mode, all the outputs are fixed to gnd. 85-88 135-138 183-186 com1 ? com4 o outputs for lcd display. connected to the common pins on the lcd panel. the output pins are located at three positions: both ends of the chip and between seg40 and seg41. each is connected inside the chip. use the com pins in accordance with the panel to be used. in the display off mode, all the outputs are fixed to gnd. when the slave is set (m/s=?l?), com1 to com4 outputs are gnd level fixed. 32-37 vdd - power supply pin for logic circuit. 38-43 vlcd - power supply pin for lcd driver. 26-31 gnd - ground pin. 16 64 vddo - vdd output pin. use this pin when fixing the mode setting input pin to "h" on the cog. 3 79 gndo - ground output pin. use this pin when fixing the mode setting input pin to "l" on the cog. 1-2 80-84 89-94 179-182 187-190 dummy - floating pin. at this time, avoid this pin from shorting with pins other than dummy in the wiring on the cog. *1: for details of the com /seg waveform when a duty is selected, refer to "common waveform" on page 18 and "common segment waveform" on page 19 to 23. *2: oscillator circuit configuration ? when m/s = "h", osc i/e = "h" [internal rf oscillation mode] [external rf oscillation mode] open osc2 osc1 oscr osc2 r osc1 open oscr
fedl9488-01 ML9488 13/31 ? external clock input mode when m/s = "h" and osc i/e = "l" ? m/s = "l", slave mode, external clock input mode *3: reset circuit configuration ? external input to restb when poceb = "h" resetb vdd external input ? poc circuit configuration when poceb = "l" resetb vdd open osc2 osc1 open oscr open external clock osc2 osc1 op en oscr op en master cko
fedl9488-01 ML9488 14/31 description operation description (seria l interface) ? display data input as described in the data configuration section, the displa y data consists of the data field that corresponds to each segment on/off and the command field that indicates the display data input. when inputting the display data, the "f3" command is set in the command field. when the "f1" or "f2" command is set in the command field, the display data in the data field becomes invalid. the data input to the data pin is loaded to the shift register at the clock pulse rise, transferred to the display data latch during the load pulse at the "h" level, then output via the segment driver. d1 d2 d3 d4 d80 c0 c1 c2 c3 c4 c5 c6 clock data new data load display output c7 data field old data command field ? display on, display off the display becomes off at power-on reset. to display, write the display on command. the display off is the command that makes all segments off. writing the display off command turns off the lights regardless of the display data. the display on is the command to release the display off. writing the display on command returns the display to the original state. d1 d2 c6 c4 c5 c6 c7 c4 c5 c6 c7 clock data load display on/off c7 reset display data input display on command write display off command write
fedl9488-01 ML9488 15/31 list of commands command name c7 c6 c5 c4 c3 c2 c1 c0 operation f0 0 0 0 0 x x x x disabled f1 0 1 f1 (*2) f0 (*2) x x x x frame frequency setting (f1,f0)=(0, 0): 130hz (f1,f0)=(0, 1): 150hz (f1,f0)=(1, 0): 170hz (f1,f0)=(1, 1): 190hz (valid for internal cr oscillation) f2 1 0 1 d (*2) x x x x display on/off "0" : off com=seg=gnd "1" : on f3(*1) 1 1 sa1 sa0 a1 a0 co1 co0 data write address setting (co1,co0)=(0, 0): corresponding to common 1 (co1,co0)=(0, 1): corresponding to common 2 (co1,co0)=(1, 0): corresponding to common 3 (co1,co0)=(1, 1): corresponding to common 4 sa1, sa0, a1, a0: chip address x: don't care (*1): for the i 2 c interface, sa1 and sa0 are set at a slave address. these bits become "don't care". (*2): the register is set to the following value by the resetb = "l" input or by the power-on poc. f1="0", f0="0", d="0" data configuration ? data configuration (serial interface) d80 d79 d78 d3 d2 d1 c0 c1 c2 c3 c4 c5 command lcd display data corresponding to seg1 corresponding to seg80 first bit c6 c7 note 1 : the commands f1 and f2 settings become valid when the least four bits of c4 to c7 are input. (the bits from d1 to d80 and from c0 to c3 are not necessary.) note 2 : if the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side. note 3 : the command execution follows the contents of the c7 to c0 registers immediately before the load becomes "h".
fedl9488-01 ML9488 16/31 ? data configuration (i 2 c interface) for the i 2 c interface, each ic is assigned with a 7-bit slave address. the first one byte in the transfer consists of this 7-bit slave address and the r/w bit that indicates the data transfer direction. always input "0" to the eighth r/w bit because the ML9488 is a write-only lsi. the eight bits next to the slave address is a control byte. the first one bit is co: consecutive command setting bit and the next one bit is rs: command/data setting bit (the remaining six bits are the don't care bits). when co = "0": means the last control byte. when co = "1": means the control bytes are successively input. when rs = "0": means the data to be input next is the command data. when rs = "1": means the data to be input next is the display data. the display data can be successively input. example of data setting ? when inputting two commands ? when inputting the command and display data r/w s 01 100 sa1 sa0 0 a co rs a msb lsb p salve address: 0 1 1 0 0 1 co: consecutive control byte setting bit 0: last control b y te , 1: consecutive control b y te rs: command/data settin g bi t 0: command data, 1: display data slave address control byte data/command when inputting two commands s 01 100 sa1 sa0 0 a 10 aa 00 aa p command command s 01 100 sa1 sa0 0 a 10 aa 01 aaa aaap display data display data command display data display data
fedl9488-01 ML9488 17/31 data write method ? serial interface the data is written to the address set by the data write setting command (f3). for the serial interface, the data is written in units of 80 bits. written from d80 to seg1, d79 to seg2, ... , d2 to seg79, and d1 to seg80. ? i 2 c interface the data is written to the address set by the slave address. for the i 2 c interface, the data is written to the specified address starting with the lsb side in units of 8 bits. (the data is written in the order from seg73-80, seg65-seg72, ... , seg9-16, and seg1-seg8.) msb segment output lsb 1234 32 33 34 35 36 37 38 39 40 com1 d80 d79 d78 d77 d49 d48 d47 d46 d45 d44 d43 d42 d41 com2 d80 d79 d78 d77 d49 d48 d47 d46 d45 d44 d43 d42 d41 com3 d80 d79 d78 d77 d49 d48 d47 d46 d45 d44 d43 d42 d41 com4 d80 d79 d78 d77 d49 d48 d47 d46 d45 d44 d43 d42 d41 msb segment output lsb 41 42 43 44 72 173 74 75 76 77 78 79 80 com1 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com2 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com3 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 com4 d40 d39 d38 d37 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb segment output msb 1234 32 33 34 35 36 37 38 39 40 com1 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com2 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com3 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com4 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 lsb segment output msb 41 42 43 44 72 73 74 75 76 77 78 79 80 com1 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com2 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com3 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8 com4 d1 d2 d3 d4 d8 d1 d2 d3 d4 d5 d6 d7 d8
fedl9488-01 ML9488 18/31 v lcd gnd v lcd gnd v lcd /2 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd v lcd /2 ? common waveforms a t 1/2-bias com4 com1 com2 com4 com3 com1 com2 com1 com3 com3 com1 com3 com2 com4 com2 com4 com1 4 (1) at static (2) at 1/2-duty a t 1/3-bias (3) at 1/3-duty (4) at 1/4-duty
fedl9488-01 ML9488 19/31 common segment output wavefor m ?at static display example on com1 off com1 com2 com3 com4 seg2 seg3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9488-01 ML9488 20/31 common and segment output waveforms ? at 1/2dut y , 1/2bias display example com1 on com2 off seg2 seg3 com1 com3 com2 com4 seg1 s e g 1 s e g 2 s e g 3 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2 v lcd gnd v lcd /2
fedl9488-01 ML9488 21/31 common and segment output waveforms ? at 1/2duty, 1/3bias display example com1 on com2 off seg2 seg3 com1 com3 com2 com4 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9488-01 ML9488 22/31 common and segment output waveforms ? at 1/3duty, 1/3bias display example com1 on com2 off com3 seg com1 com2 com4 com3 seg1 seg2 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9488-01 ML9488 23/31 common and se g ment out p ut waveforms ? at 1/4duty, 1/3bias display example com1 com2 on com3 off com4 seg2 seg3 com4 com1 com2 com3 seg1 v lcd gnd 2v lcd /3 v lcd /3 s e g 1 s e g 2 s e g 3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3 v lcd gnd 2v lcd /3 v lcd /3
fedl9488-01 ML9488 24/31 example of application circuit cascade configuration 1 serial in terface internal cr oscillator circuit used 1/4duty resetb pin is open. the common outputs of the slave chip output gnd-level. so com1 to com4 set to open. [external component] cp = 0.1 [f] (bypass capacitor between power supplies) m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg80 com2 com3 com4 cko data ML9488 master) gnd m/s vlcd bias duty0 duty1 i2c load clock sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg80 com2 com3 com4 cko data ML9488 (slave) gnd 5v 5v 5v 5v open open open open open open cpu liquid crystal panel 1/4-duty x 80 x n segments open cp cp cp cp poceb poceb sa1 sa1 mode mode open open
fedl9488-01 ML9488 25/31 cascade configuration 2 ii 2 c interface external rf-based cr oscillator circuit used 1/4duty external resetb signal input the common outputs of the slave chip output gnd-level. so com1 to com4 set to open. [external component] cp = 0.1 [f] (bypass capacitor between power supplies), rf = 470 [k ? ] (external r, resistor for cr oscillator circuit), rup = resistor for sda data bus pull-up m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg80 com2 com3 com4 cko sda ML9488 master) gnd m/s vlcd bias duty0 duty1 i2c load scl sdaack sa0 a1 a0 osci/e osc1 osc2 oscr resetb vdd test1 com1 syncb seg1 seg80 com2 com3 com4 cko sda ML9488 (slave) gnd 5v 5v open open open open cpu liquid crystal panel1/4duty 80 n open rf 5v 5v 5v cp cp cp cp poceb rup poceb sa1 sa1 mode mode
fedl9488-01 ML9488 26/31 pad configuration pad layout (pattern face) c hip size : 4.80 mm x 0.90 mm chip thickness : 400 ? m 20 ? m minimum bump pitch : 50 ? m bump height : 15 ? m 3 ? m 180 93 1 81 y x b a 181 92 190 82 ( 0,0) bump and alignment mark dimensions (pattern face) p ad no.1 ? 81 : 32 ? m x 80 ? m pad no.82 ? 190 : 30 ? m x 84 ? m alignment marks a and b : see below [mark a] [mark b] alignment mark x-coordinate ( ? m) y-coordinate ( ? m) mark a 2289 -308 mark b -2289 309 aluminum (top metal) passivation 30 m 30 m 30 m 30 m 30 m 30 m aluminum (top metal) passivation 47 m 55 m 47 m 55 m coordinate position coordinate position
fedl9488-01 ML9488 27/31 pad center coordinates pad number pad name x-coordinate (? m) y-coordinate (? m) pad number pad name x-coordinate (? m) y-coordinate (? m) 1 dummy -2206 -308 41 vlcd 27 -308 2 dummy -2149 -308 42 vlcd 81 -308 3 gndo -2092 -308 43 vlcd 135 -308 4 duty1 -2035 -308 44 resetb 192 -308 5 duty1 -1978 -308 45 resetb 244 -308 6 duty0 -1921 -308 46 osc1 298 -308 7 duty0 -1869 -308 47 osc1 350 -308 8 a0 -1815 -308 48 osc1 404 -308 9 a0 -1763 -308 49 osc2 458 -308 10 a1 -1709 -308 50 osc2 510 -308 11 a1 -1657 -308 51 osc2 564 -308 12 sa0 -1603 -308 52 osc2 618 -308 13 sa0 -1549 -308 53 oscr 672 -308 14 sa1 -1492 -308 54 oscr 724 -308 15 sa1 -1436 -308 55 oscr 776 -308 16 vddo -1379 -308 56 cko 830 -308 17 sdaack -1322 -308 57 cko 882 -308 18 sdaack -1265 -308 58 cko 934 -308 19 sdaack -1208 -308 59 cko 986 -308 20 data(sda) -1151 -308 60 syncb 1040 -308 21 data(sda) -1094 -308 61 syncb 1092 -308 22 clock(scl) -1037 -308 62 syncb 1144 -308 23 clock(scl) -980 -308 63 syncb 1196 -308 24 load -923 -308 64 vddo 1250 -308 25 load -866 -308 65 i2c 1304 -308 26 gnd -809 -308 66 i2c 1356 -308 27 gnd -752 -308 67 m/s 1413 -308 28 gnd -695 -308 68 m/s 1465 -308 29 gnd -638 -308 69 poceb 1522 -308 30 gnd -581 -308 70 poceb 1574 -308 31 gnd -524 -308 71 osci/e 1628 -308 32 vdd -467 -308 72 osci/e 1680 -308 33 vdd -412 -308 73 bias 1737 -308 34 vdd -357 -308 74 bias 1789 -308 35 vdd -302 -308 75 test2 1846 -308 36 vdd -247 -308 76 test2 1900 -308 37 vdd -192 -308 77 test1 1957 -308 38 vlcd -135 -308 78 test1 2014 -308 39 vlcd -81 -308 79 gndo 2071 -308 40 vlcd -27 -308 80 dummy 2128 -308
fedl9488-01 ML9488 28/31 pad number pad name x-coordinate (? m) y-coordinate (? m) pad number pad name x-coordinate (? m) y-coordinate (? m) 81 dummy 2185 -308 125 seg31 585 309 82 dummy 2289 -232 126 seg32 535 309 83 dummy 2289 -182 127 seg33 485 309 84 dummy 2289 -132 128 seg34 435 309 85 com1 2289 -82 129 seg35 385 309 86 com2 2289 -32 130 seg36 335 309 87 com3 2289 18 131 seg37 285 309 88 com4 2289 68 132 seg38 235 309 89 dummy 2289 118 133 seg39 185 309 90 dummy 2289 168 134 seg40 135 309 91 dummy 2289 218 135 com1 85 309 92 dummy 2289 268 136 com2 35 309 93 dummy 2185 309 137 com3 -15 309 94 dummy 2135 309 138 com4 -65 309 95 seg1 2085 309 139 seg41 -115 309 96 seg2 2035 309 140 seg42 -165 309 97 seg3 1985 309 141 seg43 -215 309 98 seg4 1935 309 142 seg44 -265 309 99 seg5 1885 309 143 seg45 -315 309 100 seg6 1835 309 144 seg46 -365 309 101 seg7 1785 309 145 seg47 -415 309 102 seg8 1735 309 146 seg48 -465 309 103 seg9 1685 309 147 seg49 -515 309 104 seg10 1635 309 148 seg50 -565 309 105 seg11 1585 309 149 seg51 -615 309 106 seg12 1535 309 150 seg52 -665 309 107 seg13 1485 309 151 seg53 -715 309 108 seg14 1435 309 152 seg54 -765 309 109 seg15 1385 309 153 seg55 -815 309 110 seg16 1335 309 154 seg56 -865 309 111 seg17 1285 309 155 seg57 -915 309 112 seg18 1235 309 156 seg58 -965 309 113 seg19 1185 309 157 seg59 -1015 309 114 seg20 1135 309 158 seg60 -1065 309 115 seg21 1085 309 159 seg61 -1115 309 116 seg22 1035 309 160 seg62 -1165 309 117 seg23 985 309 161 seg63 -1215 309 118 seg24 935 309 162 seg64 -1265 309 119 seg25 885 309 163 seg65 -1315 309 120 seg26 835 309 164 seg66 -1365 309 121 seg27 785 309 165 seg67 -1415 309 122 seg28 735 309 166 seg68 -1465 309 123 seg29 685 309 167 seg69 -1515 309 124 seg30 635 309 168 seg70 -1565 309
fedl9488-01 ML9488 29/31 pad number pad name x-coordinate (? m) y-coordinate (? m) pad number pad name x-coordinate (? m) y-coordinate (? m) 169 seg71 -1615 309 170 seg72 -1665 309 171 seg73 -1715 309 172 seg74 -1765 309 173 seg75 -1815 309 174 seg76 -1865 309 175 seg77 -1915 309 176 seg78 -1965 309 177 seg79 -2015 309 178 seg80 -2065 309 179 dummy -2115 309 180 dummy -2165 309 181 dummy -2289 203 182 dummy -2289 153 183 com4 -2289 103 184 com3 -2289 53 185 com2 -2289 3 186 com1 -2289 -47 187 dummy -2289 -97 188 dummy -2289 -147 189 dummy -2289 -197 190 dummy -2289 -247
fedl9488-01 ML9488 30/31 revision history page document no. issue date previous edition new edition description fedl9488-01 jan .15, 2013 ? ? final edition 1 issued
fedl9488-01 ML9488 31/31 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsib ility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human in jury (such as a medical instrument, transportation equipment, aerospace machinery, nucl ear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for an y such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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